Advanced Hardware Design Challenge
A concise set of eight expert-level questions probing the intricacies of processor pipelines, memory technologies, and system-level interfaces.
Quiz Questions
Answer all questions below and test your knowledge.
- 1
Which instruction set architecture introduced variable-length encoding to improve code density while maintaining backward compatibility with its predecessor?
- 2
In a modern CPU pipeline, which stage is primarily responsible for resolving branch predictions before the execution stage?
- 3
Which cache coherence protocol uses a "silent upgrade" to transition a line from Shared to Modified without broadcasting an invalidation?
- 4
What is the nominal voltage of DDR5 SDRAM per pin, and how does it compare to DDR4?
- 5
Which PCIe generation introduced a raw signaling rate of 32 GT/s per lane, effectively doubling the bandwidth of its predecessor?
- 6
In UEFI firmware, which subsystem provides the abstraction layer that allows operating systems to interface with the platform’s boot services?
- 7
When configuring a multi-socket server, which interconnect topology minimizes latency for cache-coherent memory accesses among CPUs?
- 8
Which voltage regulator architecture is most commonly used on high‑performance graphics cards to achieve fine‑grained power control across GPU cores?
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